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page 1 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet the tomodachi series of non-isolated dc-dc converters deliver exceptional electrical and thermal performance in dosa based footprints for point-of-load converters. operating from a 4.5vdc-14.4vdc input, thes e are the converters of choice for intermediate bus architecture (iba) and distributed power architecture applications that require high efficiency, tight regulation, and high reliability in elevated tem perature environments with low airflow. the tunable loop? feature allows the user to optimize the dynamic response of the converter to match the load with reduced amount of output capacitance leading to savings on cost and pwb area. the fgls12sr6040*a converter of the tomodachi series delivers 40a of out put current at a tightly regulated programmable output voltage of 0.6vdc to 2.0vdc. the thermal performance of the fgls12sr6040*a is best-in-class: little derating is needed up to 85 , under natural convection. applications ? intermediate bus architecture ? telecommunications ? data/voice processing ? distributed power architecture ? computing (servers, workstations) ? test equipments features ? compliant to rohs eu directive 2011/65/eu ? delivers up to 40a (80w) ? high efficiency, no heatsink required ? negative and positive on/off logic ? dosa based ? small size: 33.02 x 13.46 x 10.9mm (1.3 in x 0.53 in x 0.429 in) ? tape & reel packaging ? programmable output voltage from 0.6v to 2.0v via external resistor ? tunable loop? to optimize dynamic output voltage response ? power good signal ? fixed switching frequen cy with capability of external synchronization ? over-current protection (non-latching) ? over-temperature protection ? remote on/off ? ability to sink and source current ? no minimum load required ? ul * 60950-1 2 nd ed. recognized, csa ? c22.2 no. 60950-1-07 certified, and vde ? (en60950-1 2 nd ed.) licensed (pending) ? iso** 9001 and iso 14001 certified manufacturing facilities * ul is a registered trademark of u nderwriters laboratories, inc. ? csa is a registered trademark of canadian standards association. ? vde is a trademark of verband de utscher elektrotechniker e.v. ** iso is a registered trademark of the in ternational organization of standards
page 2 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet absolute maximum ratings stresses in excess of the absolute maximum ratings ma y lead to degradation in performance and reliability of the converter and may result in permanent damage. electrical specifications all specifications apply over specif ied input voltage, output load, and temper ature range, unless otherwise noted. parameter notes min typ max units input voltage continuous -0.3 15 vdc operating temperature ambient temperature -40 85 c storage temperature -55 125 c output voltage 0.6 2.0 vdc parameter notes min typ max units input characteristics operating input voltage range 4.5 14.4 vdc maximum input current vin=4.5v to 14v, io=max 24 adc input no load current vout=2.0v 104 ma vout=0.6v 54.7 ma input stand-by current vin=12v, module disabled 12.5 ma inrush transient, i 2 t 1 a 2 s input reflected-ripple current peak-to-peak (5hz to 20mhz, 1uh source impedance; vin=0 to 14v, io=max 90 map-p input ripple rejection (120hz) -60 db
page 3 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet electrical specifications (continued) parameter notes min typ max units output characteristics output voltage set point (no load) with 0.1% tolerance for external resistor used to set output voltage -1.0 +1.0 %vout output voltage range (over all operating input voltage, resistive load and temperature conditions until end of life) -3.0 +3.0 %vout adjustment range (selected by an external resistor) some output voltages may not be possible depending on the input voltage ? see feature description section 0.6 2.0 vdc remote sense range 0.5 vdc output regulation line (vin = min to max) 6 mv load (io = min to max) 10 mv temperature (ta = min to max) 0.4 %vout output ripple and noise vin=12v, io= min to max, co = 0.1uf+22uf ceramic capacitors peak to peak 5mhz to 20mhz bandwidth 50 100 mvp-p rms 5mhz to 20mhz bandwidth 20 38 mvrms external load capacitance 1 plus full load (resistive) % without the tunable loop esr 1m ? 6x47 6x47 uf with the tunable loop esr 0.15m ? 6x47 7,000 uf esr 10m ? 6x47 8,500 uf output current range (in either sink or source mode) 0 40 adc output current limit inception (hiccup mode) current limit does not operate in sink mode 150 % io-max output short-circuit current vo 250mv, hiccup mode 2.1 arms efficiency vin = 12vdc, ta = 25c, io = max vout=1.8vdc 91.5 % vout=1.2vdc 88.5 % vout=0.6vdc 81.3 % switching frequency 400 khz frequency synchronization synchronization frequency range 350 480 khz high level input voltage vih 2.0 v low level input voltage vil 0.4 v input current, sync 100 na minimum pulse width, sync 100 ns maximum sync rise time 100 ns 1 external capacitors may requi re using the new tunable loop tm feature to ensure that the module is stable as well as getting the best transient response. see the tunable loop tm section for details.
page 4 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet general specifications feature specifications parameter notes min typ max units calculated mtbf io = 0.8 io-max, ta = 40c telecordia issue 2 method 1 case 3 6,498,438 hours weight 11.7 (0.41) g (oz.) parameter notes min typ max units on/off signal interface vin = min to max, open collector or equivalent, signal reference to gnd positive logic logic high (module on) input high current 10 ua input high voltage 3.5 vin-max v logic low (module off) input low current 1 ma input low voltage -0.3 0.4 v negative logic on/off pin is open collector/drain logic input with external pull-up resistor; signal reference to gnd logic high (module off) input high current 1 ma input high voltage 2 vin-max v logic low (module on) input low current 10 ua input low voltage -0.2 0.4 v turn-on delay time full resistive load with vin (module enabled, then vin applied) fr om vin=vin(min) to 0.1*vout(nom) 1.1 ms with enable (vin applied, then enabled) from enable to 0.1*vout(nom) 700 us rise time (full resistive load) from 0. 1*vout(nom) to 0.9*vout(nom) 1.5 ms output voltage overshoot ta = 25c, vin = min to max, iout = min to max, with or without external capacitance 3.0 %vout
page 5 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet feature specifications (continued) parameter notes min typ max units over temperature protection 145 c tracking accuracy (power-up: 0.5v/ms) 100 mv (power-down: 0.5v/ms) 100 mv input under voltage lockout turn-on threshold 4.25 vdc turn-off threshold 3.96 vdc hysteresis 0.25 vdc power good overvoltage threshold for pgood on 108 %vout overvoltage threshold for pgood off 110 %vout undervoltage threshold for pgood on 92 %vout undervoltage threshold for pgood off 90 %vout pulldown resistance of pgood pin 50 ? sink current capability into pgood pin 5 ma
page 6 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet design considerations input filtering the fgls12sr6040*a converters should be connected to a low ac-impedance source. a highly inductive source can affect the stability of the module. an input capacitance must be placed directly adjacent to the input pin of the module, to minimize input ripple voltage and ensure module stability. to minimize input voltage ripple, ceramic capacitors are recommended at the input of the module. fig-1 shows the input ripple voltage for various output voltages at 40a of load current with 4x22uf, 6x22uf or 8x22uf ceramic capacitors and an input of 12v. output filtering the fgls12sr6040*a is designed for low output ripple voltage and will meet the maximum output ripple specification with 0.1uf ceramic and 47uf ceramic capacitors at the output of the module. however, additional output filtering may be required by the system designer for a number of reasons. first, there may be a need to further reduce the output ripple and noise of the module. second, the dynamic response characteristics may need to be customized to a particular load step change. to reduce the output ripple and improve the dynamic response to a step load change, additional capacitance at the output can be used. low esr polymer and ceramic capacitors are recommended to improve the dynamic respons e of the module. fig-2 provides output ripple information for different external capacitance values at various vo and a full load current of 40a. for stable operation of the module, limit the capacitance to less than the maximum output capacitance as specified in the electrical specification table. optimal performance of the module can be achieved by using the tunable loop tm feature described later in this data sheet. safety consideration for safety agency approval the power module must be installed in compliance with the spacing and separation requirements of the end-use safety agency standards, i.e., ul 60950-1 2nd, csa c22.2 no. 60950-1-07, din en 60950-1:2006 + a11 (vde0805 teil 1 + a11):2009-11; en 60950-1:2006 + a11:2009-03. for the converter output to be considered meeting the requirements of safety extra-low voltage (selv), the input must meet selv requirements. the power module has extra-low voltage (elv) outputs when all inputs are elv. the input to these units is to be provided with a fast-acting fuse with a maximum rating of 30a, 100v (for example, littlefuse 456 series) in the positive input lead. 50 100 150 200 250 300 350 400 0.60.811.21.41.61.82 ripple voltage (mvpk-pk) output voltage (volts) 4x22uf ext cap 6x22uf ext cap 8x22uf ext cap fig-1: input ripple voltage for various output voltages with various ceramic capacitors at the input (40a load). input voltage is 12v. scope bandwidth limited to 20mhz. 0 10 20 30 40 0.6 0.8 1 1.2 1.4 1.6 1.8 2 ripple (mvp-p) output voltage(volts) 6x47uf ext cap 8x47uf ext cap 10x47uf ext cap fig-2: output ripple voltage for various output voltages with external 6x47uf, 8x47uf or 10x47uf ceramic capacitors at the output (40a load). input voltage is 12v. scope bandwidth limited to 20mhz.
page 7 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet feature descriptions remote on/off the fgls12sr6040*a power modules feature an on/off pin for remote on/off operation. two on/off logic options are available. in the positive logic on/off option, (device code suffix ?p? - see part number system), the module turns on during a logic high on the on/off pin and turns off during a logic low. with the negative logic on/off option, (device code suffix ?n? - see part number system), the module turns off during logic high and on during logic low. the on/off signal should be always referenced to ground. for either on/off logic option, leaving the on/off pin disconnected will turn the module on when input voltage is present. for positive logic modules, the circuit configuration for using the on/off pin is shown in fig-3. for negative logic on/off modules, the circuit configuration is shown in fig-4. monotonic start-up and shut-down the module has monotonic start-up and shutdown behavior for any combination of rated input voltage, output current and operatin g temperature range. startup into pre-biased output the module can start into a prebiased output as long as the prebias voltage is 0.5v less than the set output voltage. output voltage programming the output voltage of the module is programmable to any voltage from 0.6dc to 2.0vdc by connecting a resistor between the trim and sig_gnd pins of the module. certain restrictions apply on the output voltage set point depending on the input voltage. these are shown in the output voltage vs. input voltage set point area plot in fig-5. the upper limit curve shows that for outpu t voltages lower than 0.8v, the input voltage must be lower than the maximum of 14.4v. the lower limit curve shows that for output voltages higher than 0.6v, the input voltage needs to be larger than the minimum of 4.5v. fig-3: circuit configuration for using positive on/off logic. mod u le internal pullup on/off i 10k pwm enable 470 on/off q1 gnd vin+ on/off 10k rpullup cr1 + _ v fig-4: circuit configuration for using negative on/off logic. pwm enable vin+ internal pullup 22k _ on/off v rpullup on/off module q1 + q3 10k i 470 gnd 10k 22k on/off fig-5: output voltage vs. input voltage set point area plot showing limits where the output voltage can be set for different input voltages. 0 2 4 6 8 10 12 14 16 0.50.70.91.11.31.51.71.92.1 i n p u t ? v o l t a g e ? ( v ) output ? voltage ? (v) upper lower
page 8 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet without an external resistor between trim and sig_gnd pins, the output of the module will be 0.6vdc. to calculate the value of the trim resistor, rtrim for a desired output voltage, should be as per the following equation: rtrim is the external resistor in k ? vo-req is the desired output voltage note that the tolerance of a trim resistor will affect the tolerance of the output voltage. standard 1% or 0.5% resistors may suffice for most applications; however, a tighter tolerance can be obtained by using two resistors in series instead of one standard value resistor. table 1 lists calculated values of r trim for common output voltages. table 1: trim resistor value v o-reg [v] r trim [k ? ] 0.6 open 0.9 40 1.0 30 1.2 20 1.5 13.33 1.8 10 remote sense the power module has a remote sense feature to minimize the effects of distribution losses by regulating the voltage between the sense pins (vs+ and vs-). the voltage drop between the sense pins and the vout and gnd pins of the module should not exceed 0.5v. voltage margining output voltage margining can be implemented in the module by connecting a resistor, rmargin-up, from the trim pin to the ground pin for margining-up the output voltage and by connecting a resistor, rmargin-down, from the trim pin to output pin for margining-down. fig-7 shows the circuit configuration for output voltage margining. the pol programming tool, available at www.fdk.com under the downloads section, also calculates t he values of rmargin-up and rmargin-down for a specific output voltage and % margin. please consult your local fdk fae for additional details. output voltage sequencing the power module includes a sequencing feature, ezsequence that enables users to implement various types of output voltage sequencing in their applications. this is accomplished via an additional sequencing pin. when not using the sequencing feature, leave it unconnected. the voltage applied to the seq pin should be scaled down by the same ratio as used to scale the output voltage down to the reference voltage of the module. this is accomplished by an external resistive divider connected across the sequencing voltage before it is fed to the seq pin as shown in fig-8. in addition, a small capacitor (suggested value 100pf) should be connected across the lower resistor r1 for all tomodachi modules, the minimum ] k [ 0.6) - (v 12 r req - o trim ? fig-6: circuit configuration for programming output voltage using and external resistor. caution ? do not connect sig_gnd to gnd elsewhere in the layout. fig-7: circuit configuration for margining output voltage.
page 9 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet recommended delay between the on/off signal and the sequencing signal is 10ms to ensure that the module output is ramped up according to the sequencing signal. this ensures that the module soft-start routine is completed before the sequencing signal is allowed to ramp up. when the scaled down sequencing voltage is applied to the seq pin, the output voltage tracks this voltage until the output reaches t he set-point voltage. the final value of the sequencing voltage must be set higher than the set-point voltage of the module. the output voltage follows the sequencing voltage on a one-to-one basis. by connecting multiple modules together, multiple modules can track their output voltages to the voltage applied on the seq pin. the module?s output can track the seq pin signal with slopes of up to 0.5v/msec during power-up or power-down. to initiate simultaneous shutdown of the modules, the seq pin voltage is lowered in a controlled manner. the output voltage of the modules tracks the voltages below their set-point voltages on a one-to-one basis. a valid input voltage must be maintained until the tracking and output voltages reach ground potential. over-current protection to provide protection in a fault (output overload) condition, the unit is equipped with internal current-limiting circuitry and can endure current limiting continuously. at t he point of current-limit inception, the unit enters hiccup mode. the unit operates normally once the output current is brought back into its specified range. over-temperature protection to provide protection in a fault condition, the unit is equipped with a thermal shutdown circuit. the unit will shut down if the over-tem perature threshold of 145c (typ) is exceeded at the thermal reference point tref. once the unit goes into thermal shutdown it will then wait to cool before attempting to restart. input under-voltage lockout (uvlo) at input voltages below the input under-voltage lockout limit, the module operation is disabled. the module will begin to operate at an input voltage above the under-voltage lockout turn-on threshold. synchronization the module switching frequen cy can be synchronized to a signal with an external frequency within a specified range. synchronization can be done by using the external signal applied to the sync pin of the module as shown in fig-i, with the converter being synchronized by the rising edge of the external signal. the electrical specifications table specifies the requirements of the external sync signal. if the sync pin is not used, the module should free run at the default switching frequency. if synchronization is not being used, connect the sync pin to gnd . active load sharing (-p option) for additional power requirements, the fgls power module is also equipped with paralleling capability. up to five modules can be configured in parallel, with active load sharing. to implement paralleling, the following conditions must be satisfied. ? all modules connected in parallel must be frequency synchronized where they are switching at the same frequency. this is done by using the sync function of the module and connecting to an external frequency source. modules can be fig-9: external source connections to synchronize switching fr equency of the module. fig-8: circuit showing connection of the sequencing signal to the seq pin.
page 10 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet interleaved to reduce input ripple/filtering requirements. ? the share pins of all units in parallel must be connected together. the path of these connections should be as direct as possible. ? the remote sense connections to all modules should be made that to the same points for the output, i.e. all vs+ and vs- terminals for all modules are connected to the power bus at the same points. some special considerations apply for design of converters in parallel operation: ? when sizing the number of modules required for parallel operation, take note of the fact that current sharing has some tolerance. in addition, under transient conditions such as a dynamic load change and during startup, all converter output currents will not be equal. to allow for such variation and avoid the likelihood of a converter shutting off due to a current overload, the total capacity of the paralleled system should be no more than 90% of the sum of the individual converters. as an example, for a system of four fgls converters in parallel, the total current drawn should be less that 90% of (3 x 40a), i.e. less than 108 a. ? all modules should be turned on and off together. this is so that all modules come up at the same time avoiding the problem of one converter sourcing current into the other leading to an overcurrent trip condition. to ensure that all modules come up simultaneously, the on/off pins of all paralleled converters should be tied together and the converters enabled and disabled using the on/off pin. note that this means that converters in parallel cannot be digitally turned on as that does not ensure that all modules being paralleled turn on at the same time. ? if digital trimming is used to adjust the overall output voltage, the adjustments need to be made in a series of small steps to avoid shutting down the output. each step should be no more than 20mv for each module. for example, to adjust the overall output voltage in a setup with two modules (a and b) in parallel from 1v to 1.1v, module a would be adjusted from 1.0 to 1.02v followed by module b from 1.0 to 1.02v, then each module in sequence from 1.02 to 1.04v and so on until the final output voltage of 1.1v is reached. ? if the sequencing function is being used to start-up and shut down modules and the module is being held to 0v by the tracking signal then there may be small deviations on the module output. this is due to controller duty cycle limitations encountered in trying to hold the voltage down near 0v. ? the share bus is not designed for redundant operation and the system will be non-functional upon failure of one of the units when multiple units are in parallel. in particular, if one of the converters shuts down dur ing operation, the other converters may also shut down due to their outputs hitting current limit. in such a situation, unless a coordinated restart is ensured, the system may never properly restart since different converters will try to re start at different times causing an overload condition and subsequent shutdown. this situation can be avoided by having an external output voltage monitor circuit that detects a shutdown condition and forces all converters to shut down and restart together. when not using the active load share feature, share pins should be left unconnected. power good the module provides a power good (pgood) signal that is implemented with an open-drain output to indicate that the output voltage is within the regulation limits of the power module. the pgood signal will be de-asserted to a low state if any condition such as over-temperature, overcurrent or loss of regulation occurs that would result in the output voltage going outside the specified thresholds. the default value of pgood on thresholds are set at 8% of the nominal vset value, and pgood off thresholds are set at 10% of the nominal vset. for example, if the nominal volt age (vset) is set at 1.0v, then the pgood on thresholds will be active anytime the output voltage is between 0.92v and 1.08v, and pgood off thresholds are active at 0.90v and 1.10v respectively. the pgood terminal can be connected through a pull-up resistor (suggested value 100k ? ) to a source of 5vdc or lower. dual layout identical dimensions and pin layout of analog and digital tomodachi modules permit migration from one to the other without needing to change the layout. in both cases the trim resistor is connected between trim and signal ground sig_gnd. tunable loop? the module has a feature t hat optimizes transient response of the module called tunable loop? external capacitors are us ually added to the output of the module for two reasons: to reduce output ripple and noise and to reduce output voltage deviations
page 11 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet from the steady-state value in the presence of dynamic load current changes. adding external capacitance however affects the voltage control loop of the module, typically causing the loop to slow down with sluggish response. larger values of external capacitance could also cause the module to become unstable. the tunable loop? allows the user to externally adjust the voltage control loop to match the filter network connected to the output of the module. the tunable loop? is implemented by connecting a series r-c between the sense and trim pins of the module, as shown in fig-10. this r-c allows the user to externally adjust the voltage loop feedback compensation of the module. recommended values of r tune and c tune for different output capacitor combinations are given in tables 2. table 2 shows the recommended values of r tune and c tune for different values of ceramic output capacitors up to 1,000uf that might be needed for an application to meet output ripple and noise requirements. selecting r tune and c tune according to table 2 will ensure stable operation of the module. in applications with tight output voltage limits in the presence of dynamic current loading, additional output capacitance will be required. table 3 lists recommended values of r tune and c tune in order to meet 2% output voltage deviation limits for some common output voltages in the presence of a 20a to 40a step change (50% of full load), with an input voltage of 12v. please contact your fdk tec hnical representative to obtain more details of this feature as well as for guidelines on how to select the right value of external r-c to tune the module for best transient performance and stable operation for other output capacitance values. table 2: general recommended value of r tune and c tune for vin=12v and various external ceramic capacitor combinations. co 6x47uf 8x47uf 10x47uf 12x47uf 20x47uf r tune 330 ? 330 ? 330 ? 330 ? 2000 ? c tune 330pf 820pf 1200pf 1500pf 3300pf table 3: recommended values of r tune and c tune to obtain transient deviation of 2% of vout for a 10a step load with vin=12v. vo 1.8v 1.2v 0.6v co 4x47uf+ 6x330uf polymer 4x47uf+ 11x330uf polymer 4x47uf+ 12x680uf polymer r tune 220 ? 200 ? 180 ? c tune 5600pf 12nf 47nf v 34mv 22mv 12mv fig-10: circuit diagram showing connection of r tune and c tune to tune the control loop of the module. note: the capacitors used in the tunable loop tables are 47uf/3m ? esr ceramic, 330uf/12 m ? esr polymer capacitor and 680uf/12m ? polymer capacitor.
page 12 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet characterization overview the converter has been characterized for several operational features, including efficiency, thermal derating (maximum available load current as a function of ambient temperature and airflow), ripple and noise, transient response to load step changes, start-up and shutdown characteristics. figures showing data plots and waveforms for different output voltages are presented in the following pages. thermal considerations power modules operate in a variety of thermal environments; however, sufficient cooling should always be provided to help ensure reliable operation. considerations include ambient temperature, airflow, module power dissipation, and the need for increased reliability. a reduction in the operating temperature of the module will result in an increase in reliability. the thermal data presented here is based on physical measurements taken in a wind tunnel. the test set-up is shown in fig-11. the preferred airflow direction for the module is in fig-12. the maximum available load current, for any given set of conditions, is defined as the lower of: (i) the output current at wh ich the temperature of any component reaches 130c, or (ii) the current rating of the converter (40a) a maximum component temperature of 120c should not be exceeded in order to operate within the derating curves. thus, the temperature at the thermocouple location shown in fig-12 should not exceed 130c in normal operation. note that continuous operation beyond the derated current as specified by the derating curves may lead to degradation in performance and reliability of the converter and may result in permanent damage. air flow x power module w ind tunnel pwbs 12.7_ (0.50) 76.2_ (3.0) probe location for measuring airflow and ambient temperature 25.4_ (1.0) fig-11: thermal test set-up fig-12: preferred airflow direction and location of hot-spot of the module (tref).
page 13 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet characteristic curves the following figures provide typical characteristic s for the 40a analog tomodachi at 1.8vo and 25c efficiency, ? (%) output current, io (a) output current, i o (a) ambient temperature, t a o c fig-13. converter efficiency versus output current. fig-14. derating output current versus ambient temperature and airflow. output voltage v o (v) (20mv/div) output current, output voltage i o (a) (20adiv) v o (v) (20mv/div) time, t (1us/div) time, t (20us /div) fig-15. typical output ripple and noise (co=6x47 f ceramic, vin = 12v, io = io,max, ). fig-16. transient response to dynamic load change from 50% to 100% at 12vin, cout= 6 x 330uf, ctune= 5.6nf & rtune= 220 ? output voltage on/off voltage v o (v) (500mv/div) v on/off (v) (5v/div) output voltage input voltage v o (v) (500mv/div) v in (v) (5v/div) time, t (1ms/div) time, t (1ms/div) fig-17. typical start-up using on/off voltage (io = io,max). fig-18. typical start-up usin g input voltage (vin = 12v, io = io,max). 70 75 80 85 90 95 100 0 10 20 30 40 vin=14.4v vin=12v vin=4.5v 5 10 15 20 25 30 35 40 45 45 55 65 75 85 95 105 2m/s (400lfm) 1.5m/s 1m/s (200lfm) 0.5m/s (100lfm) nc standard part (85c) ruggedized (d) part (105c)
page 14 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet characteristic curves the following figures provide typical characteristic s for the 40a analog tomodachi at 1.2vo and 25c efficiency, ? (%) output current, io (a) output current, i o (a) ambient temperature, t a o c fig-19. converter efficiency versus output current. fig-20. derating output current versus ambient temperature and airflow. output voltage v o (v) (10mv/div) output current, output voltage i o (a) (20adiv) v o (v) (20mv/div) time, t (1us/div) time, t (20us /div) fig-21. typical output ripple and noise (co=6x47 f ceramic, vin = 12v, io = io,max, ). fig-22. transient response to dynamic load change from 50% to 100% at 12vin, cout= 6x330uf, ctune= 12nf & rtune= 200 ? output voltage on/off voltage v o (v) (500mv/div) v on/off (v) (5v/div) output voltage input voltage v o (v) (500mv/div) v in (v) (5v/div) time, t (1ms/div) time, t (1ms/div) fig-23. typical start-up using on/off voltage (io = io,max). fig-24. typical start-up using input voltage (vin = 12v, io = io,max). 70 75 80 85 90 95 0 10203040 vin=14.4v vin=12v vin=4.5v 10 15 20 25 30 35 40 45 45 55 65 75 85 95 105 2m/s (400lfm) 1.5m/s (300lfm) 1m/s (200lfm) 0.5m/s (100lfm) nc standard part (85c) ruggedized (d) part (105c)
page 15 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet characteristic curves the following figures provide typical characteristic s for the 40a analog tomodachi at 0.6vo and 25c efficiency, ? (%) output current, io (a) output current, i o (a) ambient temperature, t a o c fig-25. converter efficiency versus output current. fig-26. derating output current versus ambient temperature and airflow. output voltage v o (v) (10mv/div) output current, output voltage i o (a) (20adiv) v o (v) (20mv/div) time, t (1us/div) time, t (20us /div) fig-27. typical output ripple and noise (co=6x47uf ceramic, vin = 12v, io = io,max, ). fig-28. transient response to dynamic load change from 50% to 100% at 12vin, cout= 12 x 680uf+6x47uf, ctune= 47nf & rtune= 180 ? output voltage on/off voltage v o (v) (200mv/div) v on/off (v) (5v/div) output voltage input voltage v o (v) (200mv/div) v in (v) (5v/div) time, t (1ms/div) time, t (1ms/div) fig-29. typical start-up using on/off voltage (io = io,max). fig-30. typical start-up usin g input voltage (vin = 12v, io = io,max). 70 75 80 85 90 0 10203040 vin=14v vin=12v vin=4.5v 15 20 25 30 35 40 45 45 55 65 75 85 95 105 2m/s (400lfm) 1.5m/s ( 300lfm ) 0.5m/s (100lfm) nc ruggedized (d) part (105c) standard part (85c) 1m/s ( 200lfm )
page 16 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet example application circuit requirements: vin: 12v vout: 1.8v iout: 30a max., worst case load transient is from 20a to 30a ? vout: 1.5% of vout (27mv) for worst case load transient vin, ripple 1.5% of vin (180mv, p-p) ci1 decoupling cap - 1x0.01uf/16v ceramic capacitor (e.g. murata lll185r71e103ma01) ci2 3x22uf/16v ceramic capacitor (e.g. murata grm32er61c226ke20) ci3 470uf/16v bulk electrolytic co1 decoupling cap - 1x0.01uf/16v ceramic capacitor (e.g. murata lll185r71e103ma01) co2 4 x 47uf/6.3v ceramic capacitor (e.g. murata grm31cr60j476me19) co3 6 x330uf/6.3v polymer (e.g. sanyo poscap) ctune 5600pf ceramic capacitor (can be 1206, 0805 or 0603 size) rtune 220 ? smt resistor (can be 1206, 0805 or 0603 size) rtrim 10k ? smt resistor (can be 1206, 0805 or 0603 size, recommended tolerance of 0.1%) vs- gnd vin+ ci3 co3 vout vs+ gnd trim ctune rtune rtrim vin co1 ci1 vout+ on/off seq modul pgood sig_gnd sync ci2 co2
page 17 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet mechanical drawing pin connections pin # function pin # function 1 on/off 11 sig_gnd 2 vin 12 vs- 3 seq 13 nc 4 gnd 14 nc 5 vout 15 sync * 6 trim 16 pg 7 vs+ 17 nc 8 gnd 18 nc 9 share 19 nc 10 gnd notes - all dimensions are in millimeters (inches) - tolerances: x.x mm ? 0.5 mm (x.xx in. ? 0.02 in.) [unless otherwise indicated] x.xx mm ? 0.25 mm (x.xxx in ? 0.010 in.) * if unused, connect to ground side view bottom view 2 8 3 4 5 6 7 9 10 11 1 12 13 14 16 17 18 19
page 18 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet recommended pad layout pin connections pin # function pin # function 1 on/off 11 sig_gnd 2 vin 12 vs- 3 seq 13 nc 4 gnd 14 nc 5 vout 15 sync * 6 trim 16 pg 7 vs+ 17 nc 8 gnd 18 nc 9 share 19 nc 10 gnd notes - all dimensions are in millimeters (inches) - tolerances: x.x mm ? 0.5 mm (x.xx in. ? 0.02 in.) [unless otherwise indicated] x.xx mm ? 0.25 mm (x.xxx in ? 0.010 in.) * if unused, connect to ground
page 19 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet packaging details the fgls modules are supplied in tape & reel as sta ndard. modules are shipped in quantities of 140 modules per reel. all dimensions are in m illimeters and (in inches). reel dimensions: outside dimensions: 330.2 mm (13.00) inside dimensions: 177.8 mm (7.00?) tape width: 56.00 mm (2.205?)
page 20 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet surface mount information pick and place the 40a analog tomodachi modules use an open frame construction and are designed for a fully automated assembly process. the modules are fitted with a label designed to provide a large surface area for pick and place operations. the label meets all the requirements for surface mount processing, as well as safety standards, and is able to withstand reflow temperatures of up to 300c. the label also carries product information such as product code, serial number and the location of manufacture. nozzle recommendations the module weight has been kept to a minimum by using open frame construction. variables such as nozzle size, tip style, vacuum pressure and placement speed should be considered to optimize this process. the minimum recommended inside nozzle diameter for reliable operation is 3mm. the maximum nozzle outer diameter, which will safely fit within the allowable component spacing, is 7mm. bottom side / first side assembly this module is not recommended for assembly on the bottom side of a customer board. if such an assembly is attempted, components may fall off the module during the second reflow process. lead free soldering the modules are lead-free (pb-free) and rohs compliant and fully compatible in a pb-free soldering process. failure to observe the instructions below may result in the failure of or cause damage to the modules and can adversely affect long-term reliability. pb-free reflow profile power systems will comply with j-std-020 rev. c (moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices) for both pb-free solder profiles and msl classification procedures. this standard provides a recommended forced-air-convection reflow profile based on the volume and thickness of t he package (table 4-2). the suggested pb-free solder paste is sn/ag/cu (sac). for questions regarding land grid array (lga) soldering, solder volume; please contact fdk for special manufacturing process instructions. the recommended linear reflow profile using sn/ag/cu solder is shown in fig-31. soldering outside of the recommended profile requires testing to verify results and performance. msl rating the 40a analog tomodachi modules have a msl rating of 2a. storage and handling the recommended storage environment and handling procedures for moisture-sensitive surface mount packages is detailed in j-std-033 rev. a (handling, packing, shipping and use of moisture / reflow sensitive surface mount de vices). moisture barrier bags (mbb) with desiccant are required for msl ratings of 2 or greater. these sealed packages should not be broken until time of use. once the original package is broken, the floor life of the product at conditions of ? 30c and 60% relative humidity varies according to the msl rating (see j-std-033a). the shelf life for dry packed smt packages will be a minimum of 12 months from the bag seal date, when stored at the following co nditions: < 40c, < 90% relative humidity. post solder cleaning and drying considerations post solder cleaning is usually the final circuit-board assembly process prior to electrical board testing. the result of inadequate cleaning and drying can affect both the reliability of a power module and the testability of the finished circuit-board assembly. for guidance on appropriate soldering, cleaning and drying procedures, refer to board mounted power modules: soldering and cleaning application note (an04-001). per j-std-020 rev. c 0 50 100 150 200 250 300 reflow time (seconds) reflow temp (c) heating zone 1c/second peak temp 260c * min. time above 235c 15 seconds *time above 217c 60 seconds cooling zone fig-31: recommended linear reflow profile using sn/ag/cu solder.
page 21 of 21 delivering next generation technology series fgls12sr6040*a 4.5-14.4vdc input, 40a, 0.6-2.0vdc output http://www.fdk.com ver 1.5 may. 9, 2013 preliminary data sheet part number system product series shape regulation input voltage mounting scheme output voltage rated current on/off logic pin shape fg l s 12 s r60 40 * a series name large s: with tracking typ=12v surface mount 0.60v (programmable: see page 7) 40a n: negative p: positive standard cautions nuclear and medical applications: fdk corporation products are not authorize d for use as critical components in life support systems, equipment used in hazardous environm ents, or nuclear control systems without the written consent of fdk corporation. specification changes and revisions: specifications are version- controlled, but are subject to change without notice.

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